The present invention relates to insulated-gate semiconductor devices incorporating electrical shorts between a device electrode and an inner semiconductor region for reducing parasitic currents, and also to a method of fabricating this type of semiconductor device.
A typical, insulated-gate semiconductor device comprises a power, insulated-gate, field-effect transistor (power IGFET). A power IGFET, in one version, includes an N.sup.+ (or highly doped N conductivity type) bulk semiconductor substrate constituting a drain region, with an N.sup.- (or lightly doped N conductivity type) epitaxial layer situated atop the N.sup.+ bulk substrate. In the upper portion of the N.sup.- epitaxial layer, a P base region is situated, and, in the upper portion of the P base region, an N.sup.+ source region, generally toroidal in shape (i.e., doughnut-shaped) is situated. A source electrode overlies the N.sup.+ source region and also the portion of the P base region in the center of the toroidally-shaped N.sup.+ source region, thereby establishing a source electrode-to-base region electrical short (hereinafter, simply "source-to-base short"). Holes (or positive charge current carriers) in the P base region are attracted to this source electrode and harmlessly enter the source electrode. This is known to reduce unwanted parasitic current in the IGFET that occurs due to the inherent N-P-N bipolar transistor contained in the IGFET and formed by the N.sup.+ drain region in combination with the N.sup.- voltage-supporting region, the P base region, and the N.sup.+ source region. A power IGFET of the foregoing type is described, for instance, in D. Kahng, editor, Applied Solid State Science-Silicon Integrated Circuits-Part B, New York: Academic Press (1981), pages 209-210.
Another insulated-gate semiconductor device comprises an insulated-gate transistor (IGT), which, in a particular configuration, is structurally similar to the foregoing IGFET except for the inclusion of a P.sup.+ drain region rather than an N.sup.+ drain region, as in the IGFET. Source-to-base shorts in an IGT prevent a particularly undesirable parasitic current: regenerative thyristor current due to the inherent P-N-P-N thyristor structure in the IGT formed by the P.sup.+ drain region, the N.sup.- voltage-supporting layer, the P base region, and the N.sup.+ source region. This parasitic current in an IGT, if unchecked by source-to-base shorts, causes the device to latch into a conductive state, with control of device current by the device gate being lost until the device current level is reduced by other means.
In both an IGFET and an IGT, it is desirable that holes in the P base region have a small maximum distance of travel to a source-to-base short. In the foregoing IGFET and IGT, holes in the P base region have a maximum distance of travel to a short that is approximately equal to the lateral width of the N.sup.+ source region as measured from a point at the inner periphery of the toroidal N.sup.+ source region to the outer periphery of the N.sup.+ source region. Unfortunately, this distance cannot be readily reduced below a minimum amount of several microns, constituting two alignment tolerances plus two N.sup.+ source lateral diffusions lengths, due to processing constraints in fabricating the devices. It would thus be desirable to provide an insulated-gate semiconductor device having source-to-base shorts with a small maximum travel length to the shorts for majority current carriers in the base region.
Insulated-gate semiconductors that are complementary in structure to the foregoing devices can be formed in which P-conductivity type semiconductor material is used in lieu of N-conductivity type material, and vice versa. Thus, the following discussion of the invention should be read with this in mind.
Accordingly, it is an object of the invention to provide an insulated-gate semiconductor device having improved source-to-base shorts in which the maximum length of travel to the shorts for holes in the P base region is smaller than in the above-described prior art devices.
Another object of the invention is to provide a method of fabricating an insulated-gate semiconductor device incorporating improved source-to-base shorts in which the shorts can be fabricated without a critically-aligned masking step.
A further object of the invention is to provide an insulated-gate semiconductor device having a low forward voltage drop.
The foregoing objects are achieved in an insulated-gate semiconductor device which, in preferred form, includes a wafer of semiconductor material, and a plurality of generally parallel gate fingers of refractory material insulatingly spaced atop the wafer. P base portions are included in the wafer and each portion is disposed between a respective pair of adjacent gate fingers. N.sup.+ source portions are included, each of which is situated within a respective P base portion and overlies a part thereof. The P base portions and N.sup.+ source portions are registered to the gate fingers in a particular, preferred embodiment resulting in an increased number of P base portions (and N.sup.+ source portions) in a device of a given size. Consequently, the device attains a low forward voltage drop. This is because each additional P base portion represents approximately the same unit of electrical resistance that is connected in parallel fashion with the other P base portions, thereby resulting in lower device resistance and, hence, lower forward voltage drop for a given device current level.
Further included in the foregoing wafer are a plurality of generally parallel P.sup.+ shorting portions that are oriented in their lengthwise directions transverse (or crosswise) to the gate fingers. The P.sup.+ shorting portions extend sufficiently far into the wafer as to adjoin the P base portions beneath the N.sup.+ source portions. The P.sup.+ shorting portions can be formed without the need for a critically-aligned masking step since they only need to be transversely oriented to the gate fingers. The P.sup.+ shorting portions are highly conductive to holes and are contacted by a source electrode so as to comprise source electrode-to-base shorts. The P.sup.+ shorting portions can be formed extremely close to each other so that holes in the P base portions have only a short maximum distance to travel to the P.sup.+ shorting portions.
In accordance with a preferred method of fabricating an insulated-gate semiconductor device having improved source-to-base shorts, there is provided a wafer of semiconductor material including a drain region overlain by an N.sup.- voltage-supporting region. P.sup.+ shorting portions are preferably then introduced into the upper portion of the N.sup.- voltage-supporting layer and are situated generally parallel to each other. The formation of the P.sup.+ shorting portions can occur subsequently in the fabrication process, however. No critical alignment step is required to form the P.sup.+ shorting portions. An insulating layer is formed atop the wafer and preferably comprises an oxide layer overlain by a layer that resists thermal oxide growth thereon, such as silicon nitride. Gate fingers of highly-doped polysilicon (N- or P- conductivity type), are formed atop the insulating layer. The gate fingers are oriented merely transverse to the P.sup.+ shorting portions and thus do not require a critical alignment step for their formation. P base portions are next formed in the wafer, each portion being situated between a respective pair of adjacent gate fingers. This is followed by formation in the wafer of N.sup.+ source portions, each being situated in a respective P base portion. The P.sup.+ shorting portions extend sufficiently far into the wafer as to adjoin the P base portions. The P.sup.+ shorting regions can be formed extremely close to each other so that the maximum travel distance for holes in the P base portions to the nearest P.sup.+ shorting region is very small.
The P base portions and N.sup.+ source portions of the device of the present fabrication method are preferably registered to the gate fingers and can be formed in this manner by implantation of suitable dopant through the insulating layer atop the wafer, which preferably comprises an oxide layer overlain by a nitride layer. With the P base portions registered to the gate fingers, many P base portions can be fabricated in a device of a given size so as to reduce the device forward voltage drop. The foregoing, preferred insulating layer is removed in two steps before metallization is applied to the upper surface of the device and appropriately patterned into source and gate regions. Drain metallization is provided on the lower surface of the drain region.